The present invention relates generally to semiconductor device processing techniques and, more particularly, to a sub-lithographic patterning method incorporating a self-aligned, single mask process.
Lithography is one of the most important techniques utilized in semiconductor manufacturing, and is particularly used to define patterns, such as those employed in a wiring layer patterning process or a doped-region defining process for example. A lithography process generally includes an exposure step and a development step, wherein the exposure step utilizes a light source to irradiate a photoresist layer directly or through a photomask to induce chemical reactions in exposed portions. The development step is conducted to remove the exposed portion in positive resist (or the unexposed portion in negative resist) and form photoresist patterns, thus completing the transfer of photomask patterns or virtual patterns to the resist material.
With lithography pushing to the theoretical limits of resolution, the use of double exposure is beginning to play a more important role. Techniques such as dipole decomposition can allow the lithographer to print features that would not be possible with a single exposure. Many of these techniques require an intermediate etch step into a hard mask material. However, the hardmask materials can have integration issues because they can interact with the substrate underneath. In addition, because the hardmask is deposited directly on the substrate, the intermediate etches can cause damage to the substrate itself. Opening the hardmask can also expose the substrate to chemicals and/or materials that adversely affect the substrate.
Alternatively, other non-conventional approaches, such as e-beam lithography and X-ray lithography, suffer the drawbacks of low throughput and immaturity for manufacturing. On the other hand, a simple sidewall spacer imaging technique transferred to a layer below allows for the formation of features narrower than the minimal size, F, that can be printed by conventional lithography, but the resulting structure is still limited by lithography capabilities, in that narrow structures spaced by lithographically defined dimensions. That is, the spacing between individual structures is not also reduced below the minimum feature size so as to allow for increased feature density.
Accordingly, it would be desirable to be able to enhance the resolution of lithographically patterned features in a manner that overcomes the above mentioned drawbacks.